This document is based on Vircon32 DevTools v24.02.04; older versions will contain inconsistencies.

Use commas to separate values (create “array” of values)

Commands that can be issued to the GPU:

Active blending:

Commands for the SPU:

States of the sound channels:

There are 64 CPU opcodes, so instructions encode them in 6 bits. No invalid opcodes can exist. HLT is opcode 0 for safety: if an empty or invalid instruction is found, the CPU will stop execution.

        IEQ,        // Integer Equal
        INE,        // Integer Not Equal
        IGT,        // Integer Greater Than
        IGE,        // Integer Greater or Equal
        ILT,        // Integer Less Than
        ILE,        // Integer Less or Equal
        
        // float comparisons
        FEQ,        // Float Equal
        FNE,        // Float Not Equal
        FGT,        // Float Greater Than
        FGE,        // Float Greater or Equal
        FLT,        // Float Less Than
        FLE,        // Float Less or Equal
        
        // data movement
        MOV,        // Move data
        LEA,        // Load effective address of a memory position
        PUSH,       // Save on top of the stack
        POP,        // Load from top of the stack
        IN,         // Read from an I/O port
        OUT,        // Write to an I/O port
        
        // string operations
        MOVS,       // Copy string (HW memcpy)
        SETS,       // Set string (HW memset)
        CMPS,       // Compare string (HW memcmp)
        
        // data conversion
        CIF,        // Convert Integer to Float
        CFI,        // Convert Float to Integer
        CIB,        // Convert Integer to Boolean
        CFB,        // Convert Float to Boolean
        
        // binary operations
        NOT,        // Bitwise NOT
        AND,        // Bitwise AND
        OR,         // Bitwise OR
        XOR,        // Bitwise XOR
        BNOT,       // Boolean NOT
        SHL,        // Bit shift left
        
        // integer arithmetic
        IADD,       // Integer Addition
        ISUB,       // Integer Subtraction
        IMUL,       // Integer Multiplication
        IDIV,       // Integer Division
        IMOD,       // Integer Modulus
        ISGN,       // Integer Sign change
        IMIN,       // Integer Minimum
        IMAX,       // Integer Maximum
        IABS,       // Integer Absolute value
        
        // float arithmetic
        FADD,       // Float Addition
        FSUB,       // Float Subtraction
        FMUL,       // Float Multiplication
        FDIV,       // Float Division
        FMOD,       // Float Modulus
        FSGN,       // Float Sign change
        FMIN,       // Float Minimum
        FMAX,       // Float Maximum
        FABS,       // Float Absolute value
        
        // extended float operations
        FLR,        // Round down
        CEIL,       // Round up
        ROUND,      // Round to nearest integer
        SIN,        // Sine
        ACOS,       // Arc cosine
        ATAN2,      // Arc Tangent from x and y
        LOG,        // Natural logarithm
        POW         // Raise to a Power
    };
    
    // -----------------------------------------------------------------------------
    
    enum class CPURegisters: int
    {
        // all 16 general-purpose registers
        Register00 = 0,
        Register01,
        Register02,
        Register03,
        Register04,
        Register05,
        Register06,
        Register07,
        Register08,
        Register09,
        Register10,
        Register11,
        Register12,
        Register13,
        Register14,
        Register15,
        
        // alternate names for specific registers
        CountRegister       = 11,
        SourceRegister      = 12,
        DestinationRegister = 13,
        BasePointer         = 14,
        StackPointer        = 15
    };
    
    // -----------------------------------------------------------------------------
    
    enum class AddressingModes : unsigned int
    {
        RegisterFromImmediate = 0,      // syntax: MOV R1, 25
        RegisterFromRegister,           // syntax: MOV R1, R2
        RegisterFromImmediateAddress,   // syntax: MOV R1, [25]
        RegisterFromRegisterAddress,    // syntax: MOV R1, [R2]
        RegisterFromAddressOffset,      // syntax: MOV R1, [R2+25]
        ImmediateAddressFromRegister,   // syntax: MOV [25], R2
        RegisterAddressFromRegister,    // syntax: MOV [R1], R2
        AddressOffsetFromRegister       // syntax: MOV [R1+25], R2
    };
    
    // -----------------------------------------------------------------------------
    
    enum class CPUErrorCodes: uint32_t
    {
        InvalidMemoryRead = 0,
        InvalidMemoryWrite,
        InvalidPortRead,
        InvalidPortWrite,
        StackOverflow,
        StackUnderflow,
        DivisionError,
        ArcCosineError,
        ArcTangent2Error,
        LogarithmError,
        PowerError
    };
}