notes:asm:circuits
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| notes:asm:circuits [2011/02/24 17:45] – created sweller5 | notes:asm:circuits [2011/03/16 16:12] (current) – syang | ||
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| + | =======Circuits======= | ||
| + | * prompt> circuitbuilder | ||
| + | * 0. and | ||
| + | * 1. or | ||
| + | * 2. inverter | ||
| + | * command: add and | ||
| + | * command: add and | ||
| + | * command: add or | ||
| + | * command: add inverter | ||
| + | * command: show | ||
| + | * current circuit | ||
| + | * composite: 4 gates, 0 in wires, 0 out wires | ||
| + | * all-in | ||
| + | * all-out | ||
| + | * and (1) | ||
| + | * in (wire 8) (wire 9) out (wire 10) | ||
| + | * -- | ||
| + | * and (2) | ||
| + | * in (wire 11) (wire 12) out (wire 13) | ||
| + | * -- | ||
| + | * or (1) | ||
| + | * in (wire 14) (wire 15) out (wire 16) | ||
| + | * -- | ||
| + | * inv (1) | ||
| + | * in (wire 17) out (wire 18) | ||
| + | * -- | ||
| + | * connections: | ||
| + | * command: connect 10 17 | ||
| + | * command: connect 18 12 | ||
| + | * command: connect 16 11 | ||
| + | * command: connect 14 8 | ||
| + | * command: connect 9 15 | ||
| + | * command: in 14 | ||
| + | * command: in 9 | ||
| + | * command: out 13 | ||
| + | * command: out 10 | ||
| + | * command: test | ||
| + | * testing composite: 4 gates, 2 in wires, 2 out wires | ||
| + | * -- | ||
| + | * 00 : 00 | ||
| + | * 10 : 10 | ||
| + | * 01 : 10 | ||
| + | * 11 : 01 | ||
| + | * -- | ||
| + | * command: stop | ||
| + | * name for circuit: half | ||
| + | * command: add half | ||
| + | * command: add half | ||
| + | * command: add or | ||
| + | * command: show | ||
| + | * current circuit | ||
| + | * composite: 3 gates, 0 in wires, 0 out wires | ||
| + | * all-in | ||
| + | * all-out | ||
| + | * composite: 4 gates, 2 in wires, 2 out wires | ||
| + | * all-in (wire 25) (wire 20) | ||
| + | * all-out (wire 24) (wire 21) | ||
| + | * output elided/ | ||
| + | * -- | ||
| + | * composite: 4 gates, 2 in wires, 2 out wires | ||
| + | * all-in (wire 36) (wire 31) | ||
| + | * all-out (wire 35) (wire 32) | ||
| + | * output elided/ | ||
| + | * -- | ||
| + | * or (4) | ||
| + | * in (wire 41) (wire 42) out (wire 43) | ||
| + | * connections: | ||
| + | * command: connect 24 31 | ||
| + | * command: connect 21 42 | ||
| + | * command: connect 32 41 | ||
| + | * command: in 36 | ||
| + | * command: in 25 | ||
| + | * command: in 20 | ||
| + | * command: out 35 | ||
| + | * command: out 43 | ||
| + | * command: test | ||
| + | * testing composite: 3 gates, 3 in wires, 2 out wires | ||
| + | * --- | ||
| + | * 0 0 0 : 0 0 | ||
| + | * 1 0 0 : 1 0 | ||
| + | * 0 1 0 : 1 0 | ||
| + | * 1 1 0 : 0 1 | ||
| + | * 0 0 1 : 1 0 | ||
| + | * 1 0 1 : 0 1 | ||
| + | * 0 1 1 : 0 1 | ||
| + | * 1 1 1 : 1 1 | ||
| + | * --- | ||
| + | command: stop | ||
| + | name for circuit: full | ||
| + | command: add | ||
| + | gate name: | ||
| + | 0. and | ||
| + | 1. or | ||
| + | 2. inverter | ||
| + | 3. half | ||
| + | 4. full | ||
| + | =====Branches===== | ||
| + | gates (clear register): ANDING 0's for all the binary sets\\ | ||
| + | gates (invert register): NOT the results for all the binary sets\\ | ||
| + | gates (copy register): EQUALS the results for all the binary sets\\ | ||
| + | gates (switching/ | ||
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