notes:sysnet
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notes:sysnet [2015/02/04 15:08] – [NES simulator] vcordes1 | notes:sysnet [2015/03/04 15:54] (current) – [sim] mp010784 | ||
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======HPC Systems and Networking====== | ======HPC Systems and Networking====== | ||
- | Notes, scratchspace, | + | Notes, scratchspace, |
- | =====NES simulator===== | + | =====Linkage===== |
- | Linkage | + | |
- | http:// | + | |
- | ====TODO==== | + | * http:// |
+ | * http:// | ||
+ | * http:// | ||
+ | * http:// | ||
- | ===ALU=== | + | =====TODO===== |
+ | |||
+ | ====ALU==== | ||
As mentioned, there are commonly 4 methods of addressing, which we will find CPUs break out separate instruction variations for: | As mentioned, there are commonly 4 methods of addressing, which we will find CPUs break out separate instruction variations for: | ||
Line 30: | Line 33: | ||
* modulus | * modulus | ||
* bit shifting | * bit shifting | ||
- | * left | + | * left bfairch2 x |
- | * right | + | * right bfairch2 x |
* bit rotation | * bit rotation | ||
- | * left | + | * left bfairch2 o |
- | * right | + | * right bfairch2 o |
* bitwise logic | * bitwise logic | ||
- | * AND | + | * AND (return in hex)bfairch2 x |
- | * OR | + | * OR |
- | * NOT | + | * NOT (return in hex)bfairch2 x |
- | * exclusive-OR (XOR, or as we may see it called: EOR) | + | * exclusive-OR (XOR, or as we may see it called: EOR) (return in hex) bfairch2 x |
* others? | * others? | ||
* flags register | * flags register | ||
Line 65: | Line 68: | ||
* Compare (basically, instigate checks that could adjust flags register bits) | * Compare (basically, instigate checks that could adjust flags register bits) | ||
- | ===datamanip=== | + | ====datamanip==== |
The **datamanip/ | The **datamanip/ | ||
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* dec2reg.sh - vcordes1 | * dec2reg.sh - vcordes1 | ||
* oct2reg.sh - vcordes1 | * oct2reg.sh - vcordes1 | ||
- | * mem2reg | + | O means it is a work in progress |
- | * hex2mem | + | x means it is finished |
- | * dec2mem | + | |
- | * oct2mem | + | due to new realizations in how the program will work, we no longer need any of the mem2 or 2mem scripts. |
- | * reg2mem | + | |
- | * oct2hex | + | * oct2hex |
- | * dec2hex | + | * dec2hex |
- | * reg2hex | + | * reg2hex |
- | * mem2hex | + | * hex2oct |
- | * hex2oct | + | * dec2oct |
- | * dec2oct | + | * reg2oct |
- | * reg2oct | + | * hex2dec |
- | * mem2oct | + | * oct2dec |
- | * hex2dec | + | * reg2dec |
- | * oct2dec | + | |
- | * reg2dec | + | * core I/O functionality |
- | * mem2dec | + | * stdin.c |
- | * core I/O functionality | + | * stdout.c |
- | * stdin.c - wedge | + | * stderr.c |
- | * stdout.c - wedge | + | |
- | * stderr.c - wedge | + | ====memory==== |
+ | ALL memory scripts will return values in octal | ||
- | ===memory=== | ||
Functionality related to memory (RAM/ROM), which the CPU treats as external and non-primary storage. | Functionality related to memory (RAM/ROM), which the CPU treats as external and non-primary storage. | ||
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The point of memget/ | The point of memget/ | ||
- | ===register=== | + | ====register==== |
Utility scripts related to registers. | Utility scripts related to registers. | ||
Line 125: | Line 128: | ||
* a simulator bootstrap script, which reads config files and creates the necessary register files (under sim/reg/) | * a simulator bootstrap script, which reads config files and creates the necessary register files (under sim/reg/) | ||
- | ===sim=== | + | ====sim==== |
The **sim/** directory is for the runtime of the configured machine in question (our 6502 CPU + related hardware components, including any " | The **sim/** directory is for the runtime of the configured machine in question (our 6502 CPU + related hardware components, including any " | ||
Line 141: | Line 144: | ||
* ops/ - simulator CPU instruction scripts | * ops/ - simulator CPU instruction scripts | ||
* named for the hex value they represent, there is one script per individual instruction. The script' | * named for the hex value they represent, there is one script per individual instruction. The script' | ||
+ | |||
+ | < | ||
+ | 0x69:ADC # | ||
+ | 0x65:ADC $%ZPAGE%: | ||
+ | 0x75:ADC $%ZPAGE%, | ||
+ | 0x6D:ADC $%ABSOL%: | ||
+ | 0x7D:ADC $%ABSOL%, | ||
+ | 0x79:ADC $%ABSOL%, | ||
+ | 0x61:ADC ($%INDIR%, | ||
+ | 0x71:ADC ($%INDIR%), | ||
+ | 0x29:AND # | ||
+ | 0x25:AND $%ZPAGE%: | ||
+ | 0x35:AND $%ZPAGE, | ||
+ | 0x2D:AND $%ABSOL%: | ||
+ | 0x3D:AND $%ABSOL%, | ||
+ | 0x39:AND $%ABSOL%, | ||
+ | 0x21:AND ($%OFFSET%, | ||
+ | 0x31:AND ($%OFFSET%), | ||
+ | 0x0A:ASL $%ACCUM%: | ||
+ | 0x06:ASL $%ZPAGE%: | ||
+ | 0x16:ASL $%ZPAGE%, | ||
+ | 0x0E:ASL $%ABSOL%: | ||
+ | 0x1E:ASL $%ABSOL%, | ||
+ | 0x90:BCC $%RELATIVE%: | ||
+ | 0xB0:BCS $%RELATIVE%2: | ||
+ | 0xF0:BEQ $%RELATIVE%2: | ||
+ | 0x24:BIT $%ZPAGE%: | ||
+ | 0x2C:BIT $%ABSOL%: | ||
+ | 0x30:BMI $%RELATIVE%: | ||
+ | 0xD0:BNE $%RELATIVE%: | ||
+ | 0x10:BPL $%RELATIVE%: | ||
+ | 0x00:BRK $%IMPL%:1:7 | ||
+ | 0x50:BVC $%RELATIVE%: | ||
+ | 0x70:BCS $%RELATIVE%: | ||
+ | 0x18:CLC $%IMPL%:1:2 | ||
+ | 0xD8:CLD $%IMPL%:1:2 | ||
+ | 0x58:CLI $%IMPL%:1:2 | ||
+ | 0xB8:CLV $%IMPL%:1:2 | ||
+ | 0xC9:CMP # | ||
+ | 0xC5:CMP $%ZPAGE%: | ||
+ | 0xD5:CMP $%ZPAGE%, | ||
+ | 0xCD:CMP $%ABSOL%: | ||
+ | 0xDD:CMP $%ABSOL%, | ||
+ | 0xD9:CMP $%ABSOL%, | ||
+ | 0xC1:CMP ($%INDIR%, | ||
+ | 0xD1:CMP ($%INDIR%), | ||
+ | 0xE0:CPX # | ||
+ | 0xE4:CPX $%ZPAGE%: | ||
+ | 0xEC:CPX $%ABSOL%: | ||
+ | 0xC0:CPY # | ||
+ | 0xC4:CPY $%ZPAGE%: | ||
+ | 0xCC:CPY $%ABSOL%: | ||
+ | 0xC6:DEC $%ZPAGE%: | ||
+ | 0xD6:DEC $%ZPAGE%, | ||
+ | 0xCE:DEC $%ABSOL%: | ||
+ | 0xDE:DEC $%ABSOL%, | ||
+ | 0xCA:DEX $%IMPL%:1:2 | ||
+ | 0x88:DEY $%IMPL%:1:2 | ||
+ | 0x49:EOR # | ||
+ | 0x45:EOR $%ZPAGE%: | ||
+ | 0x55:EOR $%ZPAGE%, | ||
+ | 0x4D:EOR $%ABSOL%: | ||
+ | 0x5D:EOR $%ABSOL%, | ||
+ | 0x59:EOR $%ABSOL%, | ||
+ | 0x41:EOR ($%INDIR%, | ||
+ | 0x51:EOR ($%INDIR%), | ||
+ | 0xE6:INC $%ZPAGE%: | ||
+ | 0xF6:INC $%ZPAGE%, | ||
+ | 0xEE:INC $%ABSOL%: | ||
+ | 0xFE:INC $%ABSOL%, | ||
+ | 0xE8:INX $%IMPL%:1:2 | ||
+ | 0xC8:INY $%IMPL%:1:2 | ||
+ | 0x4C:JMP $%ABSOL%: | ||
+ | 0x6C:JMP ($%INDIR%): | ||
+ | 0x20:JSR $%ABSOL%: | ||
+ | 0xA9:LDA # | ||
+ | 0xA5:LDA $%ZPAGE%: | ||
+ | 0xB5:LDA $%ZPAGE%, | ||
+ | 0xAD:LDA $%ABSOL%: | ||
+ | 0xBD:LDA $%ABSOL%, | ||
+ | 0xB9:LDA $%ABSOL%, | ||
+ | 0xA1:LDA ($%INDIR%, | ||
+ | 0xB1:LDA ($%INDIR%), | ||
+ | 0xA2:LDX # | ||
+ | 0xA6:LDX $%ZPAGE%: | ||
+ | 0xB6:LDX $%ZPAGE%, | ||
+ | 0xAE:LDX $%ABSOL%: | ||
+ | 0xBE:LDX $%ABSOL%, | ||
+ | 0xA0:LDY # | ||
+ | 0xA4:LDY $%ZPAGE%: | ||
+ | 0xB4:LDY $%ZPAGE%, | ||
+ | 0xAC:LDY $%ABSOL%: | ||
+ | 0xBC:LDY $%ABSOL%, | ||
+ | 0x4A:LSR $%ACCUM%: | ||
+ | 0x46:LSR $%ZPAGE%: | ||
+ | 0x56:LSR $%ZPAGE%, | ||
+ | 0x4E:LSR $%ABSOL%: | ||
+ | 0x5E:LSR $%ABSOL%, | ||
+ | 0xEA:NOP $%IMPL%:1:2 | ||
+ | 0x09:ORA # | ||
+ | 0x05:ORA $%ZPAGE%: | ||
+ | 0x15:ORA $%ZPAGE%, | ||
+ | 0x0D:ORA $%ABSOL%: | ||
+ | 0x1D:ORA $%ABSOL%, | ||
+ | 0x19:ORA $%ABSOL%, | ||
+ | 0x01:ORA ($%INDIR%, | ||
+ | 0x11:ORA ($%INDIR%), | ||
+ | 0x48:PHA $%IMPL%:1:3 | ||
+ | 0x08:PHP $%IMPL%:1:3 | ||
+ | 0x68:PLA $%IMPL%:1:4 | ||
+ | 0x28:PLP $%IMPL%:1:4 | ||
+ | 0x2A:ROL $%ACCUM%: | ||
+ | 0x26:ROL $%ZPAGE%: | ||
+ | 0x36:ROL $%ZPAGE%, | ||
+ | 0x2E:ROL $%ABSOL%: | ||
+ | 0x3E:ROL $%ABSOL%: | ||
+ | 0x6A:ROR $%ACCUM%: | ||
+ | 0x66:ROR $%ZPAGE%: | ||
+ | 0x76:ROR $%ZPAGE%, | ||
+ | 0x6E:ROR $%ABSOL%: | ||
+ | 0x7E:ROR $%ABSOL%: | ||
+ | 0x40:RTI $%IMPL%:1:6 | ||
+ | 0x60:RTS $%IMPL%: | ||
+ | 0xE9:SBC wedge (in class) | ||
+ | 0xE5:SBC $%ZPAGE%: | ||
+ | 0xF5:SBC $%ZPAGE%, | ||
+ | 0xED:SBC $%ABSOL%: | ||
+ | 0xFD:SBC $%ABSOL%, | ||
+ | 0xF9:SBC $%ABSOL%, | ||
+ | 0xE1:SBC ($%INDIR%, | ||
+ | 0xF1:SBC ($%INDIR%), | ||
+ | 0x38:SEC $%IMPL%:1:2 | ||
+ | 0xF8:SED $%IMPL%: | ||
+ | 0x78:SEI $%IMPL%:1:2 | ||
+ | Ox85:STA $%ZPAGE%: | ||
+ | 0x95:STA $%ZPAGE%, | ||
+ | 0x8D:STA $%ABSOL%: | ||
+ | 0x9D:STA $%ABSOL%, | ||
+ | 0x99:STA $%ABSOL%, | ||
+ | 0x81:STA ($%INDIR%, | ||
+ | 0x91:STA ($%INDIR%), | ||
+ | 0x86:STX $%ZPAGE%: | ||
+ | 0x96:STX $%ZPAGE%, | ||
+ | 0x8E:STX $%ABSOL%: | ||
+ | 0x84:STY $%ZPAGE%: | ||
+ | 0x94:STY $%ZPAGE%, | ||
+ | 0x8C:STY $%ABSOL%: | ||
+ | 0xAA:TAX wedge (in class) | ||
+ | 0xA8:TAY mp010784 | ||
+ | 0xBA:TSX dshadeck | ||
+ | 0x8A:TXA mp010784 | ||
+ | 0x9A:TXS dshadeck | ||
+ | 0x98:TYA mp010784 | ||
+ | </ | ||
* code/ - programs to run on the simulator | * code/ - programs to run on the simulator | ||
* sbin/ - simulator binaries... the scripts and compiled sources of the various utility functions | * sbin/ - simulator binaries... the scripts and compiled sources of the various utility functions | ||
- | ====Development approach==== | + | =====Development approach===== |
To acclimate everyone, we will be covering the basics, and attempting to provide everyone with ample opportunities to have a hand in helping to implement core simulator functionality. | To acclimate everyone, we will be covering the basics, and attempting to provide everyone with ample opportunities to have a hand in helping to implement core simulator functionality. | ||
notes/sysnet.1423080537.txt.gz · Last modified: 2015/02/04 15:08 by vcordes1