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notes:sysnet [2015/02/13 18:44] – [ALU] bfairch2 | notes:sysnet [2015/03/04 20:54] (current) – [sim] mp010784 | ||
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* modulus | * modulus | ||
* bit shifting | * bit shifting | ||
+ | * left bfairch2 x | ||
+ | * right bfairch2 x | ||
+ | * bit rotation | ||
* left bfairch2 o | * left bfairch2 o | ||
* right bfairch2 o | * right bfairch2 o | ||
- | * bit rotation | ||
- | * left | ||
- | * right | ||
* bitwise logic | * bitwise logic | ||
* AND (return in hex)bfairch2 x | * AND (return in hex)bfairch2 x | ||
Line 216: | Line 216: | ||
0xE8:INX $%IMPL%:1:2 | 0xE8:INX $%IMPL%:1:2 | ||
0xC8:INY $%IMPL%:1:2 | 0xC8:INY $%IMPL%:1:2 | ||
- | 0x4C:JMP $%ABSOL%: | + | 0x4C:JMP $%ABSOL%: |
- | 0x6C:JMP ($%INDIR%): | + | 0x6C:JMP ($%INDIR%): |
0x20:JSR $%ABSOL%: | 0x20:JSR $%ABSOL%: | ||
0xA9:LDA # | 0xA9:LDA # | ||
Line 266: | Line 266: | ||
0x7E:ROR $%ABSOL%: | 0x7E:ROR $%ABSOL%: | ||
0x40:RTI $%IMPL%:1:6 | 0x40:RTI $%IMPL%:1:6 | ||
- | 0x60:RTS $%IMPL%:1:6 | + | 0x60:RTS $%IMPL%: |
0xE9:SBC wedge (in class) | 0xE9:SBC wedge (in class) | ||
- | 0xE5:SBC $%ZPAGE%:2:3 | + | 0xE5:SBC $%ZPAGE%:2:3784 |
0xF5:SBC $%ZPAGE%, | 0xF5:SBC $%ZPAGE%, | ||
0xED:SBC $%ABSOL%: | 0xED:SBC $%ABSOL%: |