Differences

This shows you the differences between two versions of the page.

--- notes:projects:make [2010/02/19 21:44] – oppenheim
+++ notes:projects:make [2010/02/19 22:18] (current) – oppenheim
@@ Line 1: / Line 1: @@
+~~NOTOC~~
+=====make=====
+click on a topic in the concept map
+{{map>:user:oppenheim:makemap.png|Concept Map}}
+[[.make#the story|the story @ 121,14,248,57]]
+[[.make#grammar|grammar @ 130,76,246,114]]
+[[.make#learning|learning @ 126,127,245,176]]
+[[.make#non-traditional uses|non-traditional uses @ 276,42,496,70]]
+{{<map}}
+====the story====
+====grammar====
+====non-traditional uses====
+====learning ====
+ok makefiles, to start comments are "#", long line can be split with the " \", tab is required after a dependency line, $(VAR) or ${VAR} for variables.
+<code>
+gcc main.c file1.c file2.c -o hello
+</code>
+is what you normaly would run to complile a program with the gcc compiler and the 3 .c file to an executable called hello.
+<code>
+#
+# Makefile for hello
+#
+# compiler: gcc
+# to compile type "make" at command line
+#
+all :
+      gcc main.c file1.c file2.c -o hello
+</code>
+this file is saved with the name "Makefile" and will compile the program hello just as if it was typed out on the command line. things to note - [target]:[dependencies] in this case the target "all" depends on everything. this looks for time stamps to save on compile time. if a dependant has a newer last changed stamp then the taget then the target needs to be recompiled else is left alone.
+<code>
+#
+# Makefile for hello
+#
+# compiler: gcc
+# to compile type "make" at command line
+#
+all : hello
+hello : main.o file1.o file2.o
+      gcc main.o file1.o file2.o -o hello
+main.o : main.c
+      echo main.c is being compiled
+      gcc -c main.c
+file1.o : file1.c
+      echo file1.c is being compiled
+      gcc -c file1.c
+file2.o : file2.c
+      echo file2.c is being compiled
+      gcc -c file2.c
+clean :
+      rm -rf *.o hello
+</code>
+this example builds alittle on what was there before. last time if there was a change to one of the files everything was recompiled. breaking everything up as shown here if only file2.c was modified on file2 would be recompiled. the clean: removes any left over executables and object files that are left over. i've also thrown in some simple echos to show that shell commands can be used as well.
+<code>
+#
+# Makefile for hello
+#
+# compiler: gcc
+# to compile type "make" at command line
+#
+CC = gcc
+CFLAGS = -c
+OBJ = main.o file1.o file2.o
+all : hello
+hello : $(OBJ)
+      $(CC) $(OBJ) -o hello
+main.o : main.c
+      echo main.c is being compiled
+      $(CC) $(CFLAGS) main.c
+file1.o : file1.c
+      echo file1.c is being compiled
+      $(CC) $(CFLAGS) main.c
+file2.o : file2.c
+      echo file2.c is being compiled
+      $(CC) $(CFLAGS) file2.c
+clean :
+      rm -rf *.o hello
+</code>
+in this extension of the makefile i added variables for everything that repeated throughout the file so that if i wanted to change lets say the compiler all i would have to do is change the CC value at the top.
+[[http://www.gnu.org/software/make/manual/make.html|Makefile documentation]]
+**NOTE: this documentation is located in two places** [[:documentation/makefile|Makefile basics]]
+if you add to this one please add to the other one as well.

Lab46 Wiki

User Tools

Site Tools

Differences

Page Tools