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======HPC Systems and Networking======
Notes, scratchspace, and collaborative wiki for our endeavors in HPC Systems and Networking -- NES Simulator

=====Linkage=====

  * http://homepage.ntlworld.com/cyborgsystems/CS_Main/6502/6502.htm
  * http://nesdev.com/6502.txt
  * http://www.thealmightyguru.com/Games/Hacking/Wiki/index.php?title=6502_Opcodes
  * http://www.obelisk.demon.co.uk/6502/reference.html

=====TODO=====

====ALU====
As mentioned, there are commonly 4 methods of addressing, which we will find CPUs break out separate instruction variations for:

  * register- register-to-register operation. Internal.
  * immediate- constant(-to-register)... ability to provide a fixed value (like the number 3), as an operand
  * memory- pull some (or all-- depends on CPU) information to be processed from memory (address provided as operand to instruction; also adds to the instruction size)
  * indirect- pull data from the memory address specified in index/pointer registers (we do not specify memory address, it has already been loaded into existing registers)

Due to the script-centric nature of the simulator, for our core ALU functionality, we really don't need to implement these specific actions... we can merely create temporary register files, loading any of this data in and then doing the register-to-register operation; but for practice individuals can choose to implement this functionality (like having an add.sh for reg-to-reg, addimm.sh for immediate, addmem.sh for memory interaction, and addind.sh for indirection).

Also, if context is unclear, always assume a register is the medium to be used.

Functionality that needs to be implemented:

  * adding (ALU/add.sh)
    * register to register - wedge
    * do we need any of the other forms with proper mangling?
  * subtracting
  * multiplication
  * division
  * modulus
  * bit shifting
    * left bfairch2 x
    * right bfairch2 x
  * bit rotation
    * left bfairch2 o
    * right bfairch2 o
  * bitwise logic
    * AND (return in hex)bfairch2 x
    * OR  (return in hex)bfairch2 x
    * NOT (return in hex)bfairch2 x
    * exclusive-OR (XOR, or as we may see it called: EOR) (return in hex) bfairch2 x
    * others?
  * flags register
    * check current state
      * zero (ALU/checkZero.sh) - wedge
      * sign
      * carry
      * overflow
      * parity
      * ...
    * set flag state
      * zero (ALU/setZero.sh)
      * sign (ALU/setSign.sh)
      * carry
      * overflow
      * parity
      * ...
    * clear flag state
      * zero (ALU/clearZero.sh)
      * sign
      * carry
      * overflow
      * parity
      * ...
  * Compare (basically, instigate checks that could adjust flags register bits)

====datamanip====
The **datamanip/** directory will contain helper programs/scripts to aid us to juggling data around, both for our interacting-with-simulator uses, but also core CPU functionality that just focuses an data manipulation, but may not otherwise invoke ALU functionality (like adjusting flags register)

  * load (datamanip/load.sh) - wedge
    * load will load a byte located at the specified memory address and output it in register format
  * store
    * store will take a byte (in register format) and store it at the specified memory address
  * data juggling -- these are largely to assist us, especially when implementing other core functionality.
    * hex2reg.sh - wedge
      * reads hex value from STDIN, outputs it in our "ASCII-ized binary" register format
    * dec2reg.sh - vcordes1
    * oct2reg.sh - vcordes1
O means it is a work in progress
x means it is finished

due to new realizations in how the program will work, we no longer need any of the mem2 or 2mem scripts.

    * oct2hex    - bfairch2 x
    * dec2hex    - bfairch2 x
    * reg2hex    - bfairch2 x
    * hex2oct    - bfairch2 x
    * dec2oct    - bfairch2 x
    * reg2oct    - bfairch2 x
    * hex2dec    - bfairch2 x
    * oct2dec    - bfairch2 x
    * reg2dec    - bfairch2 x

  * core I/O functionality 
    * stdin.c    - wedge
    * stdout.c   - wedge
    * stderr.c   - wedge

====memory====
ALL memory scripts will return values in octal

Functionality related to memory (RAM/ROM), which the CPU treats as external and non-primary storage.

It is stored in a binary file (in an attempt to conceptually distinguish it from the "easy-to-read" ASCII-ized binary of our registers), so we have to access it in more specific ways

  * memget.sh - wedge
    * may not be fully functional, likely needs some tweaks
    * basically, we provide it with the path to the memory file and the address, and it should produce a byte of information (in register format?)
  * memgetbyte.c - wedge
    * an attempt at (re-)implementing core memory interactions. This program specifically will grab and return (in hex) the byte of memory at indicated memory address
    * logic currently assumes all bytes are 8-bits (not really a problem for our current endeavor)
  * meminit.sh - wedge
    * bootstrap script on simulator start that will read simulator config files and generate appropriate memory files (and initialize to initial values? All zeros right now)
  * memput.sh - wedge
    * the opposite of memget; memput will take a byte of data from a register and is responsible for placing it into memory at an indicated address

The point of memget/memput is that all other simulator functions needing to interact with memory should rely on these to do their heavy lifting. Nothing else should touch memory but these. Everything else that needs it uses these scripts.

====register====
Utility scripts related to registers.

  * regdisp.sh - wedge
    * yes, little more than a **cat** of an indicated register file, but as is the spirit with the memget/memput, EVERYTHING should use regdisp.sh to display the contents of the register (many of the samples I already wrote do not do this, so they will need to be updated accordingly)
  * reginit.sh - wedge
    * a simulator bootstrap script, which reads config files and creates the necessary register files (under sim/reg/)

====sim====
The **sim/** directory is for the runtime of the configured machine in question (our 6502 CPU + related hardware components, including any "software" we wish to run on them).

It consists of several subdirectories:

  * etc/ - simulator config files
    * instructions.conf - mapping of hex opcodes to assembly mneumonics and instruction size/cycle info
      * this is meant as a database to assist with simulator operations (and reference for us when implementing things)
    * io.conf - mapping of memory addresses to I/O; a way of letting us hook device access into memory
    * memory.conf - memory layout
    * registers.conf - register layout
    * simulator.conf - intended top-level config for simulator
    * simvar.sh - bootstrap script setting important variables
      * may also provide some simulator-environment library functions
  * ops/ - simulator CPU instruction scripts
    * named for the hex value they represent, there is one script per individual instruction. The script's purpose is to use the existing scripts/programs (ALU, datamanip, memory, register, etc.) along with whatever specific logic is necessary to accomplish the desired task at hand)

<code>
0x69:ADC #$%IMMED%:2:2 - wedge
0x65:ADC $%ZPAGE%:2:3
0x75:ADC $%ZPAGE%,X:2:4
0x6D:ADC $%ABSOL%:3:4
0x7D:ADC $%ABSOL%,X:3:4+1
0x79:ADC $%ABSOL%,Y:3:4+1
0x61:ADC ($%INDIR%,X):2:6
0x71:ADC ($%INDIR%),Y:2:5+1
0x29:AND #$%IMMED%:2:2
0x25:AND $%ZPAGE%:2:3
0x35:AND $%ZPAGE,X%:2:4
0x2D:AND $%ABSOL%:3:4
0x3D:AND $%ABSOL%,X:3:4+1
0x39:AND $%ABSOL%,Y:3:4+1
0x21:AND ($%OFFSET%,X):2:6
0x31:AND ($%OFFSET%),Y:2:5+1
0x0A:ASL $%ACCUM%:1:2
0x06:ASL $%ZPAGE%:2:5
0x16:ASL $%ZPAGE%,X:2:6
0x0E:ASL $%ABSOL%:3:6
0x1E:ASL $%ABSOL%,X:3:7
0x90:BCC $%RELATIVE%:2:2+1/2+2
0xB0:BCS $%RELATIVE%2:2+1/2+2
0xF0:BEQ $%RELATIVE%2:2+1/2+2
0x24:BIT $%ZPAGE%:2:3
0x2C:BIT $%ABSOL%:3:4
0x30:BMI $%RELATIVE%:2:2+1/2+2
0xD0:BNE $%RELATIVE%:2:2+1/2+2
0x10:BPL $%RELATIVE%:2:2+1/2+2
0x00:BRK $%IMPL%:1:7
0x50:BVC $%RELATIVE%:2:2+1/2+2
0x70:BCS $%RELATIVE%:2:2+1/2+2
0x18:CLC $%IMPL%:1:2
0xD8:CLD $%IMPL%:1:2
0x58:CLI $%IMPL%:1:2
0xB8:CLV $%IMPL%:1:2
0xC9:CMP #$%IMMED%:2:2
0xC5:CMP $%ZPAGE%:2:3
0xD5:CMP $%ZPAGE%,X:2:4
0xCD:CMP $%ABSOL%:3:4
0xDD:CMP $%ABSOL%,X:3:4+1
0xD9:CMP $%ABSOL%,Y:3:4+1
0xC1:CMP ($%INDIR%,X):2:6
0xD1:CMP ($%INDIR%),Y:2:5+1
0xE0:CPX #$%IMMED%:2:2
0xE4:CPX $%ZPAGE%:2:3
0xEC:CPX $%ABSOL%:3:4
0xC0:CPY #$%IMMED%:2:2
0xC4:CPY $%ZPAGE%:2:3
0xCC:CPY $%ABSOL%:3:4
0xC6:DEC $%ZPAGE%:2:5
0xD6:DEC $%ZPAGE%,X:2:6
0xCE:DEC $%ABSOL%:3:6
0xDE:DEC $%ABSOL%,X:3:7
0xCA:DEX $%IMPL%:1:2
0x88:DEY $%IMPL%:1:2
0x49:EOR #$%IMMED%:2:2
0x45:EOR $%ZPAGE%:2:3
0x55:EOR $%ZPAGE%,X:2:4
0x4D:EOR $%ABSOL%:3:4
0x5D:EOR $%ABSOL%,X:3:4+1
0x59:EOR $%ABSOL%,Y:3:4+1
0x41:EOR ($%INDIR%,X):2:6
0x51:EOR ($%INDIR%),Y:2:5+1
0xE6:INC $%ZPAGE%:2:5
0xF6:INC $%ZPAGE%,X:2:6
0xEE:INC $%ABSOL%:3:6
0xFE:INC $%ABSOL%,X:3:7
0xE8:INX $%IMPL%:1:2
0xC8:INY $%IMPL%:1:2
0x4C:JMP $%ABSOL%:3:3 (dshadeck)
0x6C:JMP ($%INDIR%):3:5 (dshadeck)
0x20:JSR $%ABSOL%:3:6
0xA9:LDA #$%IMMED%:2:2
0xA5:LDA $%ZPAGE%:2:3
0xB5:LDA $%ZPAGE%,X:2:4
0xAD:LDA $%ABSOL%:3:4
0xBD:LDA $%ABSOL%,X:3:4+1
0xB9:LDA $%ABSOL%,Y:3:4+1
0xA1:LDA ($%INDIR%,X):2:6
0xB1:LDA ($%INDIR%),Y:2:5+1
0xA2:LDX #$%IMMED%:2:2
0xA6:LDX $%ZPAGE%:2:3
0xB6:LDX $%ZPAGE%,Y:2:4
0xAE:LDX $%ABSOL%:3:4
0xBE:LDX $%ABSOL%,Y:3:4+1
0xA0:LDY #$%IMMED%:2:2
0xA4:LDY $%ZPAGE%:2:3
0xB4:LDY $%ZPAGE%,X:2:4
0xAC:LDY $%ABSOL%:3:4
0xBC:LDY $%ABSOL%,X:3:4+1
0x4A:LSR $%ACCUM%:1:2
0x46:LSR $%ZPAGE%:2:5
0x56:LSR $%ZPAGE%,X:2:6
0x4E:LSR $%ABSOL%:3:6
0x5E:LSR $%ABSOL%,X:3:7
0xEA:NOP $%IMPL%:1:2
0x09:ORA #$%IMMED%:2:2
0x05:ORA $%ZPAGE%:2:3
0x15:ORA $%ZPAGE%,X:2:4
0x0D:ORA $%ABSOL%:3:4
0x1D:ORA $%ABSOL%,X:3:4+1
0x19:ORA $%ABSOL%,Y:3:4+1
0x01:ORA ($%INDIR%,X):2:6
0x11:ORA ($%INDIR%),Y:2:5+1
0x48:PHA $%IMPL%:1:3
0x08:PHP $%IMPL%:1:3
0x68:PLA $%IMPL%:1:4
0x28:PLP $%IMPL%:1:4
0x2A:ROL $%ACCUM%:1:2
0x26:ROL $%ZPAGE%:2:5
0x36:ROL $%ZPAGE%,X:2:6
0x2E:ROL $%ABSOL%:3:6
0x3E:ROL $%ABSOL%:3:7	
0x6A:ROR $%ACCUM%:1:2
0x66:ROR $%ZPAGE%:2:5
0x76:ROR $%ZPAGE%,X:2:6
0x6E:ROR $%ABSOL%:3:6
0x7E:ROR $%ABSOL%:3:7
0x40:RTI $%IMPL%:1:6
0x60:RTS $%IMPL%:1:6   mp010784
0xE9:SBC wedge (in class)
0xE5:SBC $%ZPAGE%:2:3784
0xF5:SBC $%ZPAGE%,X:2:4
0xED:SBC $%ABSOL%:3:4
0xFD:SBC $%ABSOL%,X:3:4+1
0xF9:SBC $%ABSOL%,Y:3:4+1
0xE1:SBC ($%INDIR%,X):2:6
0xF1:SBC ($%INDIR%),Y:2:5+1
0x38:SEC $%IMPL%:1:2
0xF8:SED $%IMPL%:1:2	
0x78:SEI $%IMPL%:1:2
Ox85:STA $%ZPAGE%:2:3
0x95:STA $%ZPAGE%,X:2:4
0x8D:STA $%ABSOL%:3:4
0x9D:STA $%ABSOL%,X:3:5
0x99:STA $%ABSOL%,Y:3:5
0x81:STA ($%INDIR%,X):2:6
0x91:STA ($%INDIR%),Y:2:6
0x86:STX $%ZPAGE%:2:3
0x96:STX $%ZPAGE%,Y:2:4
0x8E:STX $%ABSOL%:3:4
0x84:STY $%ZPAGE%:2:3
0x94:STY $%ZPAGE%,X:2:4
0x8C:STY $%ABSOL%:3:4
0xAA:TAX wedge (in class)
0xA8:TAY mp010784
0xBA:TSX dshadeck
0x8A:TXA mp010784
0x9A:TXS dshadeck
0x98:TYA mp010784	
</code>
  * code/ - programs to run on the simulator
  * sbin/ - simulator binaries... the scripts and compiled sources of the various utility functions

=====Development approach=====
To acclimate everyone, we will be covering the basics, and attempting to provide everyone with ample opportunities to have a hand in helping to implement core simulator functionality.

Sort of the tinderbox approach (exposure to ideas that may spark understanding)

Each week we may stop and focus on a particular aspect of the simulator (such as take an instruction, and suss out what needs to happen for it to work).

The general trend is that this stuff is so stupidly simple and obvious it is hard to comprehend just how simple and obvious it is. We are used to things being far more complex.

That is one of the things I love about Computer Organization / this project... I get to see people experiencing those moments of clarity, and slowly realizing more and more what is going on (the stark simplicity, but vast redundancy of the whole thing).