Differences

This shows you the differences between two versions of the page.

--- documentation:makefile [2010/02/18 15:45] – triley2
+++ documentation:makefile [2010/12/17 21:47] (current) – mgough
@@ Line 1: / Line 1: @@
+=====Makefile=====
+Typical configurations for makefiles.
+Note: The code below are just examples, you must modify them to work with your own software.
+Makefile component identification.
+  *# - comments
+  *\ - splits long lines
+  *tab - required after depenancy lines (ie: [target : dependancy], enter, tab over)
+  *$() or ${} - both work as variable identifiers
+<cli>
+gcc main.c file1.c file2.c -o hello
+</cli>
+The above is what you normally would run to compile a program with the gcc compiler and the 3 .c file to an executable called hello.
+<code make>
+#
+# Makefile for hello
+#
+# compiler: gcc
+# to compile type "make" at command line
+#
+all :
+      gcc main.c file1.c file2.c -o hello
+</code>
+This file is saved with the name "Makefile". It will compile the program hello, but without typing the entire gcc line out on the command line.
+Things to note - [target]:[dependencies] in this case, the target "all" depends on everything. This looks for time stamps to save on compile time. If a dependent has a newer last changed stamp then the target then the target needs to be recompiled else is left alone.
+<code make>
+#
+# Makefile for hello
+#
+# compiler: gcc
+# to compile type "make" at command line
+#
+all : hello
+hello : main.o file1.o file2.o
+      gcc main.o file1.o file2.o -o hello
+main.o : main.c
+      echo main.c is being compiled
+      gcc -c main.c
+file1.o : file1.c
+      echo file1.c is being compiled
+      gcc -c file1.c
+file2.o : file2.c
+      echo file2.c is being compiled
+      gcc -c file2.c
+clean :
+      rm -rf *.o hello
+</code>
+This example builds a little on what was there before. last time if there was a change to one of the files everything was recompiled. breaking everything up as shown here if only file2.c was modified on file2 would be recompiled. the clean: removes any left over executable and object files. I have also thrown in some simple echos to show that shell commands can be used as well.
+<code make>
+#
+# Makefile for hello
+#
+# compiler: gcc
+# to compile type "make" at command line
+#
+CC = gcc
+CFLAGS = -c
+OBJ = main.o file1.o file2.o
+all : hello
+hello : $(OBJ)
+      $(CC) $(OBJ) -o hello
+main.o : main.c
+      echo main.c is being compiled
+      $(CC) $(CFLAGS) main.c
+file1.o : file1.c
+      echo file1.c is being compiled
+      $(CC) $(CFLAGS) main.c
+file2.o : file2.c
+      echo file2.c is being compiled
+      $(CC) $(CFLAGS) file2.c
+clean :
+      rm -rf *.o hello
+</code>
+In this version of the makefile I have added variables for everything that is repeated throughout the file. If you then wanted to change lets say the compiler all i would have to do is change the CC value at the top.
+**asm Makefile**
+An example of a make file for use in assembly language.
+<code make>
+#
+# Makefile for asm
+# name: Makefile
+# to run "make" at cli
+#
+CC = gcc
+CC2 = nasm
+PROG = first
+OBJ = driver.c asm_io.o first.o
+CFLAGS = -f elf -d ELF_TYPE
+$(PROG) : $(OBJ)
+      $(CC) $(OBJ) -o $(PROG)
+asm_io.o :
+      $(CC2) $(CFLAGS) asm_io.o
+$(PROG).o : $(PROG).asm
+      $(CC2) $(CFLAGS) $(PROG).asm
+</code>
+  *[[http://www.gnu.org/software/make/manual/make.html|GNU Make]] - documentation