documentation:makefile
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documentation:makefile [2010/02/18 13:56] – triley2 | documentation:makefile [2010/12/17 21:47] (current) – mgough | ||
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+ | =====Makefile===== | ||
+ | Typical configurations for makefiles. | ||
+ | |||
+ | Note: The code below are just examples, you must modify them to work with your own software. | ||
+ | |||
+ | Makefile component identification. | ||
+ | *# - comments | ||
+ | *\ - splits long lines | ||
+ | *tab - required after depenancy lines (ie: [target : dependancy], | ||
+ | *$() or ${} - both work as variable identifiers | ||
+ | |||
+ | <cli> | ||
+ | gcc main.c file1.c file2.c -o hello | ||
+ | </ | ||
+ | |||
+ | The above is what you normally would run to compile a program with the gcc compiler and the 3 .c file to an executable called hello. | ||
+ | |||
+ | <code make> | ||
+ | # | ||
+ | # Makefile for hello | ||
+ | # | ||
+ | # compiler: gcc | ||
+ | # to compile type " | ||
+ | # | ||
+ | all : | ||
+ | gcc main.c file1.c file2.c -o hello | ||
+ | </ | ||
+ | |||
+ | This file is saved with the name " | ||
+ | |||
+ | Things to note - [target]: | ||
+ | |||
+ | |||
+ | <code make> | ||
+ | # | ||
+ | # Makefile for hello | ||
+ | # | ||
+ | # compiler: gcc | ||
+ | # to compile type " | ||
+ | # | ||
+ | all : hello | ||
+ | |||
+ | hello : main.o file1.o file2.o | ||
+ | gcc main.o file1.o file2.o -o hello | ||
+ | | ||
+ | main.o : main.c | ||
+ | echo main.c is being compiled | ||
+ | gcc -c main.c | ||
+ | |||
+ | file1.o : file1.c | ||
+ | echo file1.c is being compiled | ||
+ | gcc -c file1.c | ||
+ | |||
+ | file2.o : file2.c | ||
+ | echo file2.c is being compiled | ||
+ | gcc -c file2.c | ||
+ | |||
+ | clean : | ||
+ | rm -rf *.o hello | ||
+ | </ | ||
+ | |||
+ | This example builds a little on what was there before. last time if there was a change to one of the files everything was recompiled. breaking everything up as shown here if only file2.c was modified on file2 would be recompiled. the clean: removes any left over executable and object files. I have also thrown in some simple echos to show that shell commands can be used as well. | ||
+ | |||
+ | |||
+ | <code make> | ||
+ | # | ||
+ | # Makefile for hello | ||
+ | # | ||
+ | # compiler: gcc | ||
+ | # to compile type " | ||
+ | # | ||
+ | |||
+ | CC = gcc | ||
+ | CFLAGS = -c | ||
+ | OBJ = main.o file1.o file2.o | ||
+ | |||
+ | all : hello | ||
+ | |||
+ | hello : $(OBJ) | ||
+ | $(CC) $(OBJ) -o hello | ||
+ | | ||
+ | main.o : main.c | ||
+ | echo main.c is being compiled | ||
+ | $(CC) $(CFLAGS) main.c | ||
+ | |||
+ | file1.o : file1.c | ||
+ | echo file1.c is being compiled | ||
+ | $(CC) $(CFLAGS) main.c | ||
+ | |||
+ | file2.o : file2.c | ||
+ | echo file2.c is being compiled | ||
+ | $(CC) $(CFLAGS) file2.c | ||
+ | |||
+ | clean : | ||
+ | rm -rf *.o hello | ||
+ | </ | ||
+ | |||
+ | In this version of the makefile I have added variables for everything that is repeated throughout the file. If you then wanted to change lets say the compiler all i would have to do is change the CC value at the top. | ||
+ | |||
+ | **asm Makefile** | ||
+ | An example of a make file for use in assembly language. | ||
+ | <code make> | ||
+ | # | ||
+ | # Makefile for asm | ||
+ | # name: Makefile | ||
+ | # to run " | ||
+ | # | ||
+ | |||
+ | CC = gcc | ||
+ | CC2 = nasm | ||
+ | PROG = first | ||
+ | OBJ = driver.c asm_io.o first.o | ||
+ | CFLAGS = -f elf -d ELF_TYPE | ||
+ | |||
+ | $(PROG) : $(OBJ) | ||
+ | $(CC) $(OBJ) -o $(PROG) | ||
+ | |||
+ | asm_io.o : | ||
+ | $(CC2) $(CFLAGS) asm_io.o | ||
+ | |||
+ | $(PROG).o : $(PROG).asm | ||
+ | $(CC2) $(CFLAGS) $(PROG).asm | ||
+ | </ | ||
+ | |||
+ | *[[http:// | ||