Table of Contents

Intel 8085

The processor of the GODS! You WISH you were as sexy and amazing as the awe inspiring squishyness that is posessed by those contributing to this processor project! Maybe if you asked nicely they'd allow you to watch as they conquer the universe…

ToDo

Who is doing what

translating the interpreter (Translator is coded, read function is next.).

8085 Subdirectory is created!

Registers

Register is started. The registers (A, B, C, D, E, H, and L) are indexed by letter. Bit selection within a register ranges from 1 to 8. Currently .set and .clear functions roughed out (may want to refine them to take individual bit entries and save with tick). The .rotate (left, insert right, and return orphaned bit) and .shift (right, insert to the left, and return orphaned bit) functions are completed and need test files. Beginnind work on the hex code commands for data transfer activities. keeping movement as a private function and the hex commands as public functions calling the move function or such as needed. Should be able to overload the move function for usage with 1, 2, and 3 byte commands. If it seems to work it can be implemented as a template for a LOT of the other commands, and will make the hassle of coding all the possibilities less so.

Interpreter (to tie things together)

TERP class (for the Interpreter)is going to get the commands and convert them to their appropriate hex code. Public functions will be:

Private will include:

Arithmetic Logic Unit

I've been looking at stuff, and I'm not sure whether we should keep a translator and an interpreter, of just make the memory accessible from the register class. and go from the interpreter straight to the register where the hex command can execute. thoughts?

The memory is accessible from the register class (I've got it included at the moment. I'm just using the interpreter to change from assembly to the actual hex instruction. So you can grab from the memory within functions and do what you want with them. The memory get and put functions are public for the memory block. –BE

Register Class

Right now the Register class contains 7 registers of 8-1bit latches each. they can be utilized individually or in pairs. The g8sr class is included so all bits are stored as boolean values. Entire bytes can be moved within the class by passing an entiry g8sr object.

The basic functions are held private.

The class will accept HEX commands (prefaced with an 'i') and execute the base command for the right register or information based on that input. Register designations within the class are alphabetical. there is a conversion function [int regConv(char)] which will assign translate the character to the proper register in the array.

Flags HAVE been implemented in the Register class, but they are currently in an array. I think it'll be smoother later if we actually use individual latches named for the apropriate flags. Flags are boolean values.

The MOV r1, r2 opcodes are coded and only need a .h updated for them.

The general functions for Logical Ops to rotate right and left, and rotate through carry right and left are coded. the HEX functions need to be done for them (with some adaptation to make the general function work I think.)

Everything I'm looking at for the Register class will require the passing of either a G8SR object or a character. maybe a translation function for input of actual 8bit data for things like the ADA M opcode? Can anyone thing of a better way to handle raw data passing?

Memory

The 256kB of memory for the 8085 is being represented by a 2 dimensional array of G8SR class objects. This means the array is 256×256 with each object conatining 8-1 bit flip flop latches or 1 Byte per object.

The MEM class has get, put, private address resolution and memory dump functionality at the moment.

Instructions

Instructions come in one, two, and three byte instructions.

Byte
One Byte Instruction
One Op Code
Two byte instruction
One Op Code
Two Data or Address
Three byte instructions
One Op Code
Two Data or
Three Address
Data Transfer Group

Condition flags are not affected by this group.

Instruction Effect
MOV r1, r2 The content of register r2 is moved to register r1
MOV r, M The content of memory location, whos address is stored in registers H and L, is moved to register r
MOV M, r The content of the register r is moved to memory loaction stored in registers H and L
MVI r, data The content of byte 2 of the instruction is moved to register r.
MVI M, data The content of byte 2 of the instruction is moved to the memory location whose address is stored in H and L
LXI rp, data 16 Byte 3 of the instruction is moved to the high order register of the register pair, byte 2 is moved to the low order register.
LDA addr content of the memory location, whose address is in byte 3 and 3 of the instruction is loaded into the accumulator
STA addr Content of the accumulator is moved to the memory location indicated in bytes 2 and 3.
LHLD addr The content of the memory location at the address in bytes 2 and 3 is loaded into register L. The content of the next memory loaction is loaded into register H.
SHLD addr The content of register L is loaded into the memory location indicated in bytes 2 and 3. The content of register H is loaded into the next memory location.
LDAX rp the content of the memory location whose address is in the register pair is moved to register A.
STAX rp The content of register A is moved to the memory address loaction stored in the register pair.
XCHG The contents of rp H-L are exchanged with the contents of register pair D-L.
Arithmetic Group
Instruction Action Flags
ADD r The content of register r is added to the accumulator and the result is placed in the accumulator Z,S,P,C,AC
ADD M The content of memory at address located in H-L is added to the accumulator and result is placed in the accumulator. Z,S,P,C,AC
ADI data The content of byte 2 is added to the accumulator and result is placed in the accumulator. Z,S,P,C,AC
ADC r The content of register r and the carry flag is added to the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
ADC M The content of the memory at location stored in H-L and the carry flag is added to the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
ACI data The content of the second byte and the carry flag are added to the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
SUB r The content of register r is subtracted from the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
SUB M The content of memory location stored in H-L is subtracted from the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
SUI data The content of the second byte is subtracted from the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
SBB r The content of the register r and the carry flag are subtracted from the accumulator, and the result is sotred in the accumulator. Z,S,P,C,AC
SBB M The content of the memory location stored in H-L and the carry flag are subtracted from the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
SBI data The content of the second byte and the carry flag are subtracted from the accumulator and the result is stored in the accumulator. Z,S,P,C,AC
INR r The content of register r is incremented by 1. Z,S,P,AC
INR M The content of memory at location stored in H-L is incremented by 1. Z,S,P,AC
DCR r The content of the register r is decrimented by 1. Z,S,P,AC
DCR M The content of memory location stored in H-L is decrimented by 1. Z,S,P,AC
INX rp The content of register pair rp is incremented by 1.
DCX rp The content of register pair rp is decrimented by 1.
DAD rp The content of register pair rp is added to the register pair H-L. If there is a carry, C is set otherwise C is reset. C
DAA The 8-bit number in the accumulator is adjusted to form two four bit Binary-Coded-Decimal digits. Z,S,P,C,AC
Logical Group
ANA r content of register r is logically ANDed with the accumulator. The result is placed in the accumulator. Z,S,P,C,AC
ANA M content of memory location whose address is stored in H-L is logically ANDed with accumulator. The result is placed in the accumulator. Z,S,P,C,AC
ANI data content of byte 2 is logically ANDed with the accumulator and the result is stored in the Accumulator.
XRA r the content of the register r is XORed with the content of the accumulator and the result is stored in the accumulator.
XRA M The content of the memory location whose address is stored in H-L is XORed with the accumulator and the result is stored in the accumulator.
XRI data The content of the second byte is XORed with A and the result is stored in A.
ORA r The content of the register r is inclusive ORed with A and the result is stored in A.
ORA M The content of the memory location whose address is stored in H-L is ORed with A and the result is stored in A.
ORI data The content of the second byte of the instruction is ORed with A and the result is stored in A.
CMP r The content of the register r is subtracted from A. A remains unchanged. Condition flags are set as a result.
CMP M The content of the memory location whose address is stored in H-L is subtracted from A. A remains unchanged. Condition flags are set.
CPI data The content of the second byte of the instruction is subtracted from the accumulator. The accumulator remains unchanged. Condition flags are set.
RLC The content of the accumulator is rotated left one position. (done needs refine for HEX)
RRC The content of the accumulator is rotated right one position. (done needs refine for HEX)
RAL Rotate left through carry. (done)
RAR Rotate right through carry. (done)
CMA The accumulator is complimented (0s become 1s and 1s become 0s)
CMC The carry flag is complimented.
STC The carry flag is set to 1.
Branch Group
JMP addr
Jcondition addr
CALL addr
Ccondition addr
RET
Rcondition
RST n
PCHL
Stack I/O and Machine Command Group
PUSH rp
PUSH PSW
POP rp
POP PSW
XTHL
SPHL
IN port
OUT port
EI
DI
HLT
NOP
RIM
SIM

Individual Commands

Data Transfer Group
Command Binary Hex
MOV A, B 01111000 0x78
MOV A, C 01111001 0x79
MOV A, D 01111010 0x7A
MOV A, E 01111011 0x7B
MOV A, H 01111100 0x7C
MOV A, L 01111101 0x7D
MOV B, A 01000111 0x47
MOV B, C 01000001 0x41
MOV B, D 01000010 0x42
MOV B, E 01000011 0x43
MOV B, H 01000100 0x44
MOV B, L 01000101 0x45
MOV C, A 01001111 0x4F
MOV C, B 01001000 0x48
MOV C, D 01001010 0x4A
MOV C, E 01001011 0x4B
MOV C, H 01001100 0x4C
MOV C, L 01001101 0x4D
MOV D, A 01010111 0x57
MOV D, B 01010000 0x50
MOV D, C 01010001 0x51
MOV D, E 01010011 0x53
MOV D, H 01010100 0x54
MOV D, L 01010101 0x55
MOV E, A 01011111 0x5F
MOV E, B 01011000 0x58
MOV E, C 01011001 0x59
MOV E, D 01011010 0x5A
MOV E, H 01011100 0x5C
MOV E, L 01011101 0x5D
MOV H, A 01100111 0x67
MOV H, B 01100000 0x60
MOV H, C 01100001 0x61
MOV H, D 01100010 0x62
MOV H, E 01100011 0x63
MOV H, L 01100101 0x65
MOV L, A 01101111 0x6F
MOV L, B 01101000 0x68
MOV L, C 01101001 0x69
MOV L, D 01101010 0x6A
MOV L, E 01101011 0x6B
MOV L, H 01101100 0x6C
MOV A, M 01111110 0x7E
MOV B, M 01000110 0x46
MOV C, M 01001110 0x4E
MOV D, M 01010110 0x56
MOV E, M 01011110 0x5E
MOV M, A 01110111 0x77
MOV M, B 01110000 0x70
MOV M, C 01110001 0x71
MOV M, D 01110010 0x72
MOV M, E 01110011 0x73
MVI A, data 00111110 0x3E
MVI B, data 00000110 0x06
MVI C, data 00001110 0x0E
MVI D, data 00010110 0x16
MVI E, data 00011110 0x1E
MVI H, data 00100110 0x26
MVI L, data 00101110 0x2E
MVI M, data 00110110 0x36
LXI B-C, data 16 00000001 0x01
LXI D-E, data 16 00010001 0x11
LXI H-L, data 16 00100001 0x21
LXI SP, data 16 00110001 0x31
LDA addr 00111010 0x3A
STA addr 00110010 0x32
LHLD addr 00101010 0x2A
SHLD addr 00100010 0x22
LDAX B-C 00001010 0x0A
LDAX D-E 00011010 0x1A
LDAX H-L 00101010 0x2A
LDAX SP 00111010 0x3A
STAX B-C 00000010 0x02
STAX D-E 00010010 0x12
STAX H-L 00100010 0x22
XCHG 11101011 0xEB
Arithmetic Group
ADD B 10000000 0x80
ADD C 10000001 0x81
ADD D 10000010 0x82
ADD E 10000011 0x83
ADD H 10000100 0x84
ADD L 10000101 0x85
ADD M 10000110 0x86
ADI data 11000110 0xC6
ADC B 10001000 0x88
ADC C 10001001 0x89
ADC D 10001010 0x8A
ADC E 10001011 0x8B
ADC H 10001100 0x8C
ADC L 10001101 0x8D
ADC M 10001110 0x8E
ACI data 11001110 0xCE
SUB B 10010000 0x90
SUB C 10010001 0x91
SUB D 10010010 0x92
SUB E 10010011 0x93
SUB H 10010100 0x94
SUB L 10010101 0x95
SUB M 10010110 0x96
SUI data 11010110 0xD6
SBB B 10011000 0x98
SBB C 10011001 0x99
SBB D 10011010 0x9A
SBB E 10011011 0x9B
SBB H 10011100 0x9C
SBB L 10011101 0x9D
SBB M 10011110 0x9E
SBI data 11011110 0xDE
INR A 00111100 0x3C
INR B 00000100 0x04
INR C 00001100 0x0C
INR D 00010100 0x14
INR E 00011100 0x1C
INR H 00100100 0x24
INR L 00101100 0x2C
INR M 00110100 0x34
DCR A 00111101 0x3D
DCR B 00000101 0x05
DCR C 00001101 0x0D
DCR D 00010101 0x15
DCR E 00011101 0x1D
DCR H 00100101 0x25
DCR L 00101101 0x2D
DCR M 00110101 0x35
INX B-C 00000011 0x03
INX D-E 00010011 0x13
INX H-L 00100011 0x23
INX SP 00110011 0x33
DCX B-C 00001011 0x0B
DCX D-E 00011011 0x1B
DCX H-L 00101011 0x2B
DCX SP 00111011 0x3B
DAD B-C 00001001 0x09
DAD D-E 00011001 0x19
DAA 00100111 0x27
Logical Group
ANA B 10100000 0xA0
ANA C 10100001 0xA1
ANA D 10100010 0xA2
ANA E 10100011 0xA3
ANA H 10100100 0xA4
ANA L 10100101 0xA5
ANA M 10100110 0xA6
ANI data 11100110 0xD6
XRA B 10101000 0xA8
XRA C 10101001 0xA9
XRA D 10101010 0xAA
XRA E 10101011 0xAB
XRA H 10101100 0xAC
XRA L 10101101 0xAD
XRA M 10101110 0xAE
XRI data 11101110 0xEE
ORA B 10110000 0xB0
ORA C 10110001 0xB1
ORA D 10110010 0xB2
ORA E 10110011 0xB3
ORA H 10110100 0xB4
ORA L 10110101 0xB5
ORA M 10110110 0xB6
ORI data 11110110 0xF6
CMP B 10111000 0xB8
CMP C 10111001 0xB9
CMP D 10111010 0xBA
CMP E 10111011 0xBB
CMP H 10111100 0xBC
CMP L 10111101 0xBD
CMP M 10111110 0xBE
CPI data 11111110 0xFE
RLC 00000111 0x05
RRC 00001111 0x0F
RAL 00010111 0x17
RAR 00011111 0x1F
CMA 00101111 0x2F
CMC 00111111 0x3F
STC 00110111 0x37
Branch Group
JMP addr 11000011 0xC3
JNZ addr 11000010 0xC2
JZ addr 11001010 0xCA
JNC addr 11010010 0xD2
JC addr 11011010 0xDA
JPO addr 11100010 0xE2
JPE addr 11101010 0xEA
JP addr 11110010 0xF2
JM addr 11111010 0xFA
CALL addr 11001101 0xCD
CNZ addr 11000100 0xC4
CZ addr 11001100 0xCC
CNC addr 11010100 0xD4
CC addr 11011100 0xDC
CPO addr 11100100 0xE4
CPE addr 11101100 0xEC
CP addr 11110100 0xF4
CM addr 11111100 0xFC
RET 11001001 0xC9
RNZ 11000000 0xC0
RZ 11001000 0xC8
RNC 11010000 0xD0
RC 11011000 0xD8
RPO 11100000 0xE0
RPE 11101000 0xE8
RP 11110000 0xF0
RM 11111000 0xF8
RST n 11nnn111 0x
PCHL 11101001 0xE9

Register Functions

regConv(char): converts the character designation for a register into the appropriate numerical designation.

clear(): Clears all registers.

clear(char): Clears a single register by ANDing all bits by 0.

clear(char, char): Clears two registers (usefull for zeroing a register pair.)

set(char, G8SR):puts a 8bit value in the designated register.

set(char, G8SR, char, G8SR): useful for loading a register pair as it puts an 8bit value in designated registers.

get(char): returns a G8SR object from the indicated register.

shift(char, bool): Shifts indicated register to the right, inserting the supplied bit to the left and returning the ejected bit.

rotate(char, bool): Rotates the indicated register to the left, inserting the supplied bit to the right and returning the ejected bit.

And: a function that ands the accumulator with another register and returns the result to the accumulator.